1. Field of the Invention
The present invention relates generally to analog-to-digital converters and control structures and methods for an analog-to-digital converter.
2. Description of the Related Art
Analog-to-digital (ADC) converters are essential components in today's electronic circuits and systems. ADC converters transform analog signals to digital signals. Conventional delta sigma (ΔΣ) analog-to-digital converters offer high resolution and linearity, high integration, little differential non-linearity, and low cost. Their performance is not limited by mismatched components within the converter, and has low noise sensitivity. Most of the circuitry in delta sigma ADCs is digital; hence the performance of delta sigma ADCs does not drift with time and temperature.
Two basic principles govern the operation of conventional delta sigma ADCs: oversampling and noise shaping. The sampling frequency in a delta sigma ADC is typically chosen to be much larger than the input signal bandwidth. Oversampling spreads the quantization noise power over a bandwidth equal to the sampling frequency. A delta sigma ADC usually contains a delta sigma modulator, a lowpass filter, and a decimator filter. The delta sigma modulator applies a lowpass filter to the input analog signal and a high pass filter to the noise, hence placing most quantization noise energy above the input signal bandwidth. The lowpass filter follows the delta sigma modulator, attenuating out-of-band quantization noise. The decimator filter downsamples the sampled output digital signal to the Nyquist rate.
Since delta sigma ADCs typically operate at an oversampled rate much larger than the maximum input signal bandwidth, their circuitry is complex and their speed is low. Because of speed limitations, delta sigma ADCs perform best in high-resolution, very-low frequency applications.
In order to successfully extend the use of delta sigma ADCs to higher frequency applications, a parallel delta sigma ADC architecture has been proposed. U.S. Pat. No. 5,196,852 by Ian Galton and “A Nyquist-Rate Delta-Sigma A/D Converter” IEEE Journal of Solid-State Circuits, Vol. 33, No. 1, pp. 45–52 describe parallel delta sigma ADC systems. The system described in U.S. Pat. No. 5,196,852 achieves an effective oversampling ratio of N*M, where N is the oversampling ratio of each delta sigma ADC and M is the number of parallel delta sigma ADC channels. The system described in “A Nyquist-Rate Delta-Sigma A/D Converter” achieves an effective oversampling ratio of M without oversampling in the individual delta sigma ADCs, where M is the number of parallel delta sigma ADC channels. However, with the circuits described in above works, the parallel delta sigma ADCs do not self-adapt. Hence, only a limited predetermined range of incoming signal frequencies can be processed.
A disclosed embodiment of the application addresses these and other issues by utilizing a parallel, adaptive delta sigma analog-to-digital converter.